How to let FPGA get access to HPS pins

Hi davidc85,

I am trying to export the UART0 from the DE1-SoC board to the FPGA but I am unable to determine how to assign the "top level" ports.. ??

As was mentioned, you get the ports for the hps component.. for the UART0 they are as follows in my top level verilog code:

// loanio uart0

.hps_0_hps_io_hps_io_gpio_inst_LOANIO61 (<connect to top level>),

.hps_0_hps_io_hps_io_gpio_inst_LOANIO62 (<connect to top level>),

//

So, I am assuming these need to be assigned to the board pins:

"HPS_UART_RX (pin_b25)" and "HPS_UART_TX (pin_c25)" respectively

My question is how you did this? .. in the pin assignents you can't choose these pins as they are reserved?

When I compile the project I get the error (for pins B25 and C25):

Error (169026): Pin HPS_UART_RX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.

Error (169026): Pin HPS_UART_TX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.

Any help is appreciated, thanks in advance. I have searched and looked for solutions here and this thread was the closest I could find and your reply above mentioned you managed to get this compiled.

other details...

Using Quartus etc version 14.0

I know how to make the preloader and linux SD Card.