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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to keep fpga in low power mode

Hello people,

Today i have another question :)

My new fpga module (with EP3C25E144) will work only when it gets a command. does its job and waits for the next command.

Because of my design has a lot of register switchings, it consumes large power even on wait mode.

My question is, How can i lower the power consumption?

I am planning to control the enable pin of crystal oscillator, i will keep it disabled while on wait state and let it be enabled when i will send a new command.

first question is, does this way work?

second question is, is there a more simple, better or any additional way for this purpose?

Regards..

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I'm not sure stopping and restarting the oscillator will work very well, as it's output can be a bit erratic when it starts again and before it stabilises.

    You can add clock enables to your design so that the registers only switch when the enable signal is active.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    That will depend on how the oscillator's clock enable works.

    Some have a "output enable" controlo, some have "power down" control.

    Anyway, you can also use a ALTCLKCTRL block to gate the clock within the FPGA.

    In addition to clock enables and clock gating, using low frequency clocks to drive parts of the logic also helps, if applicable.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    the power consumption of ocillator is not important for me. device won't work with battery. i i can keep fpga in reset, that will be enough for me. also for using clock enable, i can wait for some seconds for the oscillator to let it be stabilized.

    today i have seen another thing.

    i will use multiple fpga configuration, passive serial (PS). it looks like if i keep nCONFIG LOW, the fpga will wait on reset state. Can i use this for lowering power consumption? also in case of the nCONFIG pin may be kept low for days or weeks. when not needed, i won't let it finish reset state. and can this damage the fpga?

    please help..