Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How to keep fpga in low power mode

Hello people, Today i have another question :) My new fpga module (with EP3C25E144) will work only when it gets a command. does its job and waits for the next command. Because of my d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

That will depend on how the oscillator's clock enable works.

Some have a "output enable" controlo, some have "power down" control.

Anyway, you can also use a ALTCLKCTRL block to gate the clock within the FPGA.

In addition to clock enables and clock gating, using low frequency clocks to drive parts of the logic also helps, if applicable.