How to implement a DRC to bomb synthesis

Question

Hey guys, our core has a few parameter we would like to implement some basic DRC for. In particular, we would like to have synthesis fail if one parameter is less than another parameter. Is there any easy way to do this?

altera_forum · Answer

In VHDL, you can use the ASSERT.  Example:  ASSERT ('0' = '0')
  REPORT "'0' is still the same as '0'"
  SEVERITY ERROR;  So long as the argument is true, the assert will execute.

altera_forum · Answer

Interesting solution. I should have mentioned that we're a verilog crew, and I don't think it has an assertion capability. I suppose we could roll a vhdl wrapper

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How to implement a DRC to bomb synthesis

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