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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to implement a DRC to bomb synthesis

Hey guys, our core has a few parameter we would like to implement some basic DRC for. In particular, we would like to have synthesis fail if one parameter is less than another parameter. Is there any...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

In VHDL, you can use the ASSERT. Example: 

ASSERT ('0' = '0')
  REPORT "'0' is still the same as '0'"
  SEVERITY ERROR;

So long as the argument is true, the assert will execute.