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Honored Contributor
Honored ContributorHow to implement a DRC to bomb synthesis
Hey guys, our core has a few parameter we would like to implement some basic DRC for. In particular, we would like to have synthesis fail if one parameter is less than another parameter. Is there any...
Altera_ForumHonored Contributor
Honored ContributorInteresting solution. I should have mentioned that we're a verilog crew, and I don't think it has an assertion capability. I suppose we could roll a vhdl wrapper
