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seamusbleu's avatar
seamusbleu
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3 years ago
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How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I'm pretty sure that's because the h2f_axi_master is connected to the fpga_m2ocm_pb m0 bus.

So my question is, can I increase the ID width on the s10_hps h2f_axi_master bus? And if so, how? If not, how do I handle the mismatch?

This forum post suggests adding an AXI bridge. But that doesn't work as the AXI bridge requires the ID widths on both sides be the same.

I also tried editing the s10 h2f_axi_master ID widths in platform designer from 4->3. This seems to work, but when I create a build with this change, reads across the h2f_axi_master bus hang. I'm guessing it has something to do with the read/write/combined issuing capability is set to 16, but needs to be changed to 8.

Can someone tell me a good way around this issue?

  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

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  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi seamusbleu


    The reason behind the question before is to rule out any possibility.


    I just got an advice from my senior that the AXI ID width of the HPS is not able to be changed.

    As for the connection you have the hang is expected as the axi transactioin is exceeding the axi id value.

    To solve the error in quartus, you could use the AXI bridge to connect the slaves and master together.

    The mismatch in the AXI ID width is still be able to be connected but in the AXI transaction you will need to bare in mind to not exceed the maximum id value of the lesser ID width.


    Regards

    Jingyang, Teh


  • seamusbleu's avatar
    seamusbleu
    Icon for New Contributor rankNew Contributor
    3 years ago

    Please show me how to use an AXI bridge to connect the slaves and masters together such that the ID widths can be different on the respective sides.

    As I stated in the original post:
    >This forum post suggests adding an AXI bridge. But that doesn't work as the AXI bridge requires the ID widths on both sides be the same.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi seamusbleu


    Sorry for suggesting that idea.

    It seems like that have added the checking of mismatch slave and master ID.

    There was an update to the IP to add in this checking.


    We could not change the slave id width of the HPS.


    The checking of the slave id width is as follow:

    Slave ID width = max master ID width + log2(number of masters)


    One of two option is

    1. To reduce the number of master connected.
    2. To reduce the master id width connected to the slave.

    Reducing the master id width to 2 you could connect up to 4 master to the slave.


    Regards

    Jingyang, Teh


  • seamusbleu's avatar
    seamusbleu
    Icon for New Contributor rankNew Contributor
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi seamusbleu


    Sorry that we could not change the AXI ID width of the HPS.


    Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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    Regards

    Jingyang, Teh