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seamusbleu's avatar
seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi seamusbleu


The reason behind the question before is to rule out any possibility.


I just got an advice from my senior that the AXI ID width of the HPS is not able to be changed.

As for the connection you have the hang is expected as the axi transactioin is exceeding the axi id value.

To solve the error in quartus, you could use the AXI bridge to connect the slaves and master together.

The mismatch in the AXI ID width is still be able to be connected but in the AXI transaction you will need to bare in mind to not exceed the maximum id value of the lesser ID width.


Regards

Jingyang, Teh