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seamusbleu's avatar
seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi seamusbleu


Sorry for suggesting that idea.

It seems like that have added the checking of mismatch slave and master ID.

There was an update to the IP to add in this checking.


We could not change the slave id width of the HPS.


The checking of the slave id width is as follow:

Slave ID width = max master ID width + log2(number of masters)


One of two option is

  1. To reduce the number of master connected.
  2. To reduce the master id width connected to the slave.

Reducing the master id width to 2 you could connect up to 4 master to the slave.


Regards

Jingyang, Teh