Forum Discussion
seamusbleu
New Contributor
New ContributorHow to handle Stratix10 HPS-to-FPGA bridge ID width mismatch
The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
So what you're saying is that there is no solution to this problem - that is not helpful.
seamusbleuNew Contributor
New ContributorPlease show me how to use an AXI bridge to connect the slaves and masters together such that the ID widths can be different on the respective sides.
As I stated in the original post:
>This forum post suggests adding an AXI bridge. But that doesn't work as the AXI bridge requires the ID widths on both sides be the same.
