How to fit 2 multipliers in one DSP block - Arria V?

In a project done using Arria V FPGA (5AGXFB1HF35I3), I'm using an IP (LPM_MULT) with the following properties:

1. dataa and datab input width - 16bit
2. result output width - 32bit
3. Signed
4. Two clock pipelines
5. With clken and aclr

I have a component with 2 multipliers and 2 adders (implementing a FIR), and since this component is instantiated many times across my design (along with other, different components that use DSP blocks), I want to save up as many DSP blocks as possible.

According to the Arria V handbook, 2 multipliers can fit in 1 DSP block:

According to the Quartus 18.1 compilation report I see that each multiplier uses 1 DSP block, instead of 2 multipliers using 1 DSP block. This causes Quartus to use all the available 920 DSP blocks.

Note: something strange that I see is that while for some instantiations of the FIR component there are 2 DSP blocks (instead of 1), for others no DSP blocks are implemented at all. Could be some kind of weird merge?

This is an issue for me since:

1. According to calculations I made, Quartus should have used far less DSP blocks. This was assuming 2 multipliers fit into 1 DSP block.
2. I need to see if my design converges (resource-wise), since my design will be implemented inside another design (that uses some DSP blocks). Therefore I need to know if there are spare DSP blocks in my design (as in my calculations).

Thank you.