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eran_el's avatar
eran_el
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3 years ago

How to fit 2 multipliers in one DSP block - Arria V?

In a project done using Arria V FPGA (5AGXFB1HF35I3), I'm using an IP (LPM_MULT) with the following properties: dataa and datab input width - 16bit result output width - 32bit Signed Two cl...
eran_el's avatar
eran_el
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

If you're talking about what they're saying here:

The following Intel® Quartus® Prime IP cores are supported for the Arria® V variable precision DSP blocks implementation:

  • LPM_MULT
  • ALTERA_MULT_ADD
  • ALTMULT_COMPLEX
  • ALTMEMMULT

Then yes, I've used the LPM_MULT IP.