Forum Discussion
eran_el
New Contributor
New ContributorHow to fit 2 multipliers in one DSP block - Arria V?
In a project done using Arria V FPGA (5AGXFB1HF35I3), I'm using an IP (LPM_MULT) with the following properties:
dataa and datab input width - 16bit
result output width - 32bit
Signed
Two cl...
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
Have you used the suggested IP cores for Arria® V variable precision DSP blocks implementation?
https://www.intel.com/content/www/us/en/docs/programmable/683213/current/operational-modes.html
Thank you
Kshitij Goel
