How to find out a Tco from TimeQuest

I thought that I can use a min and max of 0 for set_input/output_delay, it just means that I give information about virtual clock and describe outside-of-FPGA clocking scheme, example of that can be seen on page 15-16 of rysc's TimeQuest User Guide (http://www.alteraforum.com/alterawiki.com/uploads/3/3f/timequest_user_guide.pdf).

Here is my whole sdc file (I changed -max and -min from 0 to 1 just for test, it changes nothing, still reported "No setup paths were found.") :

# **************************************************************

# Create Clock

# **************************************************************

create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK}]

create_clock -name {CLK_EXT_output_side} -period 5.000 -waveform { 0.000 2.500 }

create_clock -name {CLK_EXT_input_side} -period 5.000 -waveform { 0.000 2.500 }

# **************************************************************

# Create Generated Clock

# **************************************************************

derive_pll_clocks

# **************************************************************

# Set Input Delay

# **************************************************************

set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din1]

set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din1]

set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din2]

set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din2]

set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din3]

set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din3]

set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din4]

set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din4]

# **************************************************************

# Set Output Delay

# **************************************************************

set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout1]

set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout1]

set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout2]

set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout2]

set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout3]

set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout3]

set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout4]

set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout4]

Thank you for your answer, sstrell!

I agree, it is an old white paper and I realized it is a classic timing analyzer which is used there.

The task is how to meet timing through a device, I mean how to calculate or view total propagation time from input pin to output pin of FPGA, like in old white paper mentioned. For I/O timing from external device of course I have to use set_input_delay and set_output_delay constraints.

I tried to follow your suggestion ("report_timing -from [get_ports din*] -to [get_ports dout*] to generate timing reports on these paths")

I added such constraints in sdc file:

# **************************************************************

# Set Input Delay

# **************************************************************

set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din1]

set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din1]

set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din2]

set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din2]

set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din3]

set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din3]

set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din4]

set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din4]

# **************************************************************

# Set Output Delay

# **************************************************************

set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout1]

set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout1]

set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout2]

set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout2]

set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout3]

set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout3]

set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout4]

set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout4]

and also write a report_timing command:

report_timing -from [get_ports {din1}] -to [get_ports {dout1}] -npaths 10 -detail full_path -panel_name {Report Timing} -multi_corner

and even just report_timing -from [get_ports {din1}] -to [get_ports {dout1}]

But I received such answer:

Report Timing: No setup paths were found.

So maybe I misunderstood your advice, but it didn't work for me now.

This is a really old white paper based off of the old timing analyzer. Are you trying to meet timing through a device or are you talking about meeting I/O timing to/from external devices? You should have set_input_delay and set_output_delay constraints in your .sdc file defining the external timing delays to/from external devices.

You can then use (based on the paper you linked):

report_timing -from [get_ports din*] -to [get_ports dout*]

to generate timing reports on these paths.