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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to determine if 2 signals are in quadrature

Hello friends,

I need to determine if two signals are precisely on 90 deg. phase. In fact, there is a xor phase comparator and I try to catch lock condition as indicator (for viewing purposes, will be a LED). Both signals are extremely low compared to CPLD capabilities 1KHz and I don't have a greater clock but I can add if required for oversampling in lock detection process. Perhaps there is another idea. Thanks in advance,

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Xor will help detection of phase difference but can't measure actual difference.

    If your signals are two sine waves (sine/cos) and known frequency then try this simple idea:

    delay one signal one sample at a time until both are equal in phase as indicated by xor and measure your delay relative to frequency to see if it is 1/4 cycle or 3/4 cycle
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    A criterion "precisely on 90 deg. phase" won't work. If you measure phase, you have to specify a phase tolerance that is accepted as locked state. To measure a phase difference in digital signal processing, you need an oversampling clock.

    If you have an analog VCO, an obvious method is to do also the phase limit comparison in the analog domain, based on the low-pass filtered XOR comparator output.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The signals are logic and located inside CPLD along with xor for detection.

    All right then, 0.1deg error. I guess oversampling with greater clock then compare against previous period. Initially a LED indicating "lock" within error would be sufficient but then I further want to transmit actual phase error to some MCU (SPI, bus, I don't know yet and/or space in CPLD).
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You may try using feedback system (I assume without loop filter as you are using CPLD, similarly any oversampling may be difficult in CPLD).

    Your input x1 feeds the XOR. Your other input x2 feeds through a delay line. The XOR output error feeds back to delay units on x2.

    The system if designed carefully should settle and lock when x1 is in phase with x2_d.

    When locked the error from XOR is the phase error(in samples).