Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe signals are logic and located inside CPLD along with xor for detection.
All right then, 0.1deg error. I guess oversampling with greater clock then compare against previous period. Initially a LED indicating "lock" within error would be sufficient but then I further want to transmit actual phase error to some MCU (SPI, bus, I don't know yet and/or space in CPLD).