how to design private IP based on qsys

Question

Hello,i am a new recruit for SOC FGPA. Lately , i want to desgin my private IP,and then connect it to hps(A9) with AXI or ST-MM bus based on Qsys. so hps can get the status of my module.but there are  a few qusetions: is the method or architecture right to get the status from fgpa?  if it's feasible,how to design my private IP with **.v( already finished), can you give some reference mannul or details.expect  your reply.

altera_forum · Answer

For starters, see this document:

http://www.altera.com/literature/hb/qts/qsys_components.pdf

and this training course:

http://www.altera.com/education/training/courses/oqsys3000

This design example is older, but still useful:

http://www.altera.com/support/examples/nios2/exm-checksum-acc.html

altera_forum · Answer

I do appreciate your help,thanks your reply!

altera_forum · Answer

If your IP doesn't need to implement security, posted writes, or any of the other features that AXI has that Avalon-MM does not have then I recommend using Avalon since it's an easier interface standard to deal with.  Here is the Avalon-MM specification:  http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Forum Discussion

how to design private IP based on qsys

3 Replies

Recent Discussions

Does altering the FPGA IO standard actually change something in hardware?

Stratix 10 GX Transceiver IO pairs

Debugging the FPGAs connected in passive serial mode

MegaWizard Plug-In Manager : ALTPLL [Corrupted in Quartus Prime Lite 25.1]

LTC Connector DE10-Standard FPGA