Altera_ForumHonored Contributor11 years agohow to design private IP based on qsys Hello,i am a new recruit for SOC FGPA. Lately , i want to desgin my private IP,and then connect it to hps(A9) with AXI or ST-MM bus based on Qsys. so hps can get the status of my module.but there are...Show More
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information