I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 bit shift register which is loaded in parallel (so that's 72 inputs). This data, when requested, is sent out via SPI. The SPI interface consists of MISO, MOSI, SCK (2 MHz) and CS. I sync. the SCK and CS signals to a 20 MHz clock (CLK) and shift out the data on the falling edge of the synchronized SCK signal (i.e. SCK_falling). Similarly, the chip is only active the synced copy of CS goes low (CS_falling). When CS_rising is 1, I load the data into the 72 bit shift register. Now, my question is, how do I properly constrain this design so it works on a real design? From my limited understanding, it seems I need to first create two clocks (SCK and CLK). I note that TimeQuest asks for the rising and falling times of the signal. Do I simply measure this on my board and enter it? In my case, I actually remember this: the rising/falling time for SCK is just 7 ns. However, for CLK it's a bit more tricky. My o-scope is only 50 MHz and the 20 MHz waveform appears quite distorted so it will be hard to measure the rise/fall times - can I just leave them out? Secondly, do I need to constraint the 72 inputs? If so, how? What about CS, MISO and MOSI? None of these have a set frequency as CS can go low and high at any time. So how does one go about constraining these?

You probably need the following constraints; 1) A clock frequency constraint for the FPGA clock. This constrains the register-to-register paths inside the FPGA. Quartus/TimeQuest use this constraint to check that your internal logic can operate at the frequency of the clock. 2) The SPI inputs are run through synchronizers correct? In that case, you can set them as false-paths. This tells TimeQuest; "These inputs do not need to be analyzed". 3) For the SPI outputs, you can give it a constraint "that the FPGA can meet". How do you know what it can meet? You put it to 10ns to start with, and then look at the report to see if it failed, and then increase it a little. 4) Where is your parallel input coming from? If you have an external device that is writing to the FPGA, then it will have a clock-to-output delay. Its that delay that you need to tell TimeQuest about, so that it can look at the timing at the FPGA input registers to see if the register setup and hold time can be met. There's a tutorial and references in this thread: http://www.alteraforum.com/forum/showthread.php?t=31457 Cheers, Dave

Hi Dave, was hoping you'd reply. :) Yes, SCK and CS are run through synchronizers but not MISO and MOSI. I'll set CS and SCK as false paths. I'll try what you suggested about MISO. Should I also sync MOSI? [actually, currently, I'm not even using MOSI but would like to know for future reference.] Regarding the parallel input. The parallel input comes from another FPGA/CPLD. How can I find out the clock-to-output delay? Where do I tell TimeQuest about this? I already went through that thread and also your PDF. I've done followed through the TimeQuest Tutorial and that also was a big help.

--- Quote Start --- Yes, SCK and CS are run through synchronizers but not MISO and MOSI. I'll set CS and SCK as false paths. I'll try what you suggested about MISO. Should I also sync MOSI? [actually, currently, I'm not even using MOSI but would like to know for future reference.] --- Quote End --- Since you know that MISO is only ever registered based on a synchronized version of SCK, you can also set that as a false path. --- Quote Start --- Regarding the parallel input. The parallel input comes from another FPGA/CPLD. How can I find out the clock-to-output delay? Where do I tell TimeQuest about this? --- Quote End --- TimeQuest for the 'other FPGA' will tell you. Look at the 'datasheet' report. Bring up the TimeQuest GUI and you'll see that report listed. The PDF that I linked to above has plenty of examples of reading that information. The clock-to-output delay from that report can also be used as your requested setting for the MOSI output, just set the requirement for the clock-to-output delay to be slightly larger than the largest value reported, and TimeQuest will be able to 'meet' that requirement. The clock-to-output delay can be adjusted slightly by Quartus by using the IOE output registers. Quartus has much more flexibility in adjusting the input delays, since there are programmable delay cells in FPGA IOE inputs. Cheers, Dave

OK, I have an update. Here is what I did, for the 'other FPGA', step by step (I did this so I could get an actual figure for the clock to output delay). The overall input/outputs are very similar to that of the design I described in my initial post except the CPLD has 72 outputs instead of inputs. It also has a fully functional SPI interface and a active-low RESET. I followed the TimeQuest Tutorial as I did this. 1) I went and created a clock of time period 50 ns (20 Mhz) and assigned the port to CLK. I named this SYSTEM_CLOCK. 2) I then went to the Set Output Delay dialog box and entered a delay of 2 ns. I chose SYSTEM_CLOCK as the clock and chose my 72 outputs. 3) I went into the Contraints menu and chose "Set False Paths". In the FROM field I put in SYSTEM_CLOCK and in the TO field I put in SCK. I did this again for CS and MOSI. I don't think I did this step quite right because in the reports I'm still told that I have 4 unconstrained inputs. Where do I tell TimeQuest that these are False Paths? http://i.imgur.com/ncyOp.png 4) I'm also told that MISO (which I call DO in the design) isn't constrained even though I did set an output delay for it. Infact, SDC Assignments/ Set Output Delay has it in the report as well. http://i.imgur.com/2eVq6.png 5) I found the clock to output delay for my outputs. Do I just use these for my other design which has 72 inputs? Will 17.968 ~= 20 ns become the input delay? http://i.imgur.com/GzPWk.png Thanks for taking the time to respond! Would have never gotten to where I am without your help!

--- Quote Start --- 1) I went and created a clock of time period 50 ns (20 Mhz) and assigned the port to CLK. I named this SYSTEM_CLOCK. 2) I then went to the Set Output Delay dialog box and entered a delay of 2 ns. I chose SYSTEM_CLOCK as the clock and chose my 72 outputs. 3) I went into the Contraints menu and chose "Set False Paths". In the FROM field I put in SYSTEM_CLOCK and in the TO field I put in SCK. I did this again for CS and MOSI. I don't think I did this step quite right because in the reports I'm still told that I have 4 unconstrained inputs. Where do I tell TimeQuest that these are False Paths? --- Quote End --- If you are creating new constraints, then you have to re-run the analysis. Personally I create the .sdc file directly, and only use the GUI for analyzing the timing. --- Quote Start --- 5) I found the clock to output delay for my outputs. Do I just use these for my other design which has 72 inputs? Will 17.968 ~= 20 ns become the input delay? --- Quote End --- I forget whether you enter them directly, or indirectly via a calculated input delay, that is why I wrote the other tutorial. Read it. The answer should be in there :) Cheers, Dave

How to constraint my design using TimeQuest?

34 Replies

Altera_Forum
Honored Contributor
13 years ago
If I design using SCK as clock, how should I synchronously load the parallel inputs? I want the inputs to be loaded when CS is high but there is no guarantee that SCK will be running when CS is high because it's not a free running clock.
Altera_Forum
Honored Contributor
13 years ago
Ah, I see your problem..
One solution would be to have the MCU send a "command" to U2 over SPI, which would be used to sample PI.

Another solution would be to feed the first bit asynchronously from PI to SO and sample the rest of the bits on the first edge of SCK.
You'd have to asynchronously generate a "first_bit" condition.

Non-verified illustrative VHDL

process(nCS, SCK) begin if nCS = '1' then first_bit <= '1'; else if rising_edge(SCK) then first_bit <= '0'; end if; end process; process(nReset, SCK) begin if nReset = '0' then tmp <= (others => '0'); else if rising_edge(SCK) then if nCS = '0' then if first_bit = '1' then tmp <= PI; else tmp <= tmp(tmp'high-1 downto tmp'low) & '0'; end if; end if; end SO <= PI(0) when nCS = '0' and first_bit = '1' else tmp(tmp'high-1) when nCS = '0' and first_bit = '0' else 'Z';

All that said, another option is take your current logic and make it output earlier.
Make "tmp" shift after a rising SCK. This should give you 250 ns more margin in SO!
Altera_Forum
Honored Contributor
13 years ago
Thank you!

Just a tiny question: you code suggests that I should use the rising edge of SCK to shift out the bit. I'm using SPI in mode 0 which means I should be shifting out bits on the falling edge of SCK. So, shouldn't I be using the falling edge of SCK?

Secondly, I was using the shift register made by Altera's mega function utility: LPM_SHIFTREG. However, this shift register clocks out data at the rising edge again. Maybe I should invert SCK to make it do on the falling edge or perhaps make my own component? What would you suggest?
Altera_Forum
Honored Contributor
13 years ago
My VHDL was merely illustrative. :)
You should use whatever edge is more convenient and gives you the most timing margin.
Ie, a quick look tell's me that in SPI mode 0, the MCU will capture the data in the rising edge of SCK.
Launching (shifting) on the rising edge should give you the biggest setup margin (one entire SCK period) but it makes it "easy" to violate the 10 ns hold requirement.
Launching on the falling edge should make it easier to meet both setup and hold requirements. So, yes, I think you should use the falling edge.

Yes, you can just invert the input clock of LPM_SHIFTREG.
Though, there isn't much point in using LPM_SHIFTREG: Quartus will infer from the behavioral description I wrote above just fine.

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How to constraint my design using TimeQuest?

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