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Altera_Forum
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14 years ago

How to constraint my design using TimeQuest?

I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you!

Just a tiny question: you code suggests that I should use the rising edge of SCK to shift out the bit. I'm using SPI in mode 0 which means I should be shifting out bits on the falling edge of SCK. So, shouldn't I be using the falling edge of SCK?

Secondly, I was using the shift register made by Altera's mega function utility: LPM_SHIFTREG. However, this shift register clocks out data at the rising edge again. Maybe I should invert SCK to make it do on the falling edge or perhaps make my own component? What would you suggest?