How to constraint my design using TimeQuest?

My VHDL was merely illustrative. :)

You should use whatever edge is more convenient and gives you the most timing margin.

Ie, a quick look tell's me that in SPI mode 0, the MCU will capture the data in the rising edge of SCK.

Launching (shifting) on the rising edge should give you the biggest setup margin (one entire SCK period) but it makes it "easy" to violate the 10 ns hold requirement.

Launching on the falling edge should make it easier to meet both setup and hold requirements. So, yes, I think you should use the falling edge.

Yes, you can just invert the input clock of LPM_SHIFTREG.

Though, there isn't much point in using LPM_SHIFTREG: Quartus will infer from the behavioral description I wrote above just fine.