How to constraint my design using TimeQuest?

Ah, I see your problem..

One solution would be to have the MCU send a "command" to U2 over SPI, which would be used to sample PI.

Another solution would be to feed the first bit asynchronously from PI to SO and sample the rest of the bits on the first edge of SCK.

You'd have to asynchronously generate a "first_bit" condition.

Non-verified illustrative VHDL

process(nCS, SCK) begin
if nCS = '1' then
first_bit <= '1';
else if rising_edge(SCK) then
first_bit <= '0';
end if;
end process;
process(nReset, SCK) begin
if nReset = '0' then
tmp <= (others => '0');
else if rising_edge(SCK) then
if nCS = '0' then
if first_bit = '1' then
tmp <= PI;
else
tmp <= tmp(tmp'high-1 downto tmp'low) & '0';
end if;
end if;
end
SO <= PI(0) when nCS = '0' and first_bit = '1' else 
tmp(tmp'high-1) when nCS = '0' and first_bit = '0' else
'Z';

All that said, another option is take your current logic and make it output earlier.

Make "tmp" shift after a rising SCK. This should give you 250 ns more margin in SO!