Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
Nope. 10 is the limit.
- Altera_Forum
Honored Contributor
This should be no problem with an even deserialization factor, just use a multiplexer and input half width with double rate to LVDS serializer respectively perform the opposite action on receive.
- Altera_Forum
Honored Contributor
Depending on how fast the clock is you may not need ALTLVDS. You can create your own deserializer/serializer using DDIO primitive but still use the LVDS pins. You will need to manually tell Quartus in assignment editor these are LVDS pins.
ALTLVDS is limited to 10. - Altera_Forum
Honored Contributor
Here's another option - implement altlvds using LEs instead of the dedicated SERDES. In this mode, you can type in any deserialization factor in the altlvds wizard. LE mode is for lower performance interfaces. But it saves you the time of creating the logic on your own.
- Altera_Forum
Honored Contributor
The said ADS6442 has up to 910 MHz data rate. I can be processed with dedicated SERDES hardware only. The half rate in two wire mode can be processed in LE with DDIO registers.