How to clock this Tranceivers based design?

Hi all,

I need to make some communication device and I want to check if this is possible with the Altera chips and the Tranceivers.

I studied different UserGuides, but I still not sure how to clock the different parts.

The problem:

I need one main controller that runs at 150Mc. It needs to control 3 or 4 Tranceivers.

For the receive side I do not see a real problem. It is about the transmit side.

Each Tranceiver must be dynamical configurable to operate at 3Gb/s, 1.5Gb/s or 750Mb/s.

So the TX Phase Compensation Fifo has to be written with 150MHz, 75MHz or 37.5MHz (20 bits per clock).

How can I clock the TX Phase Compensation fifo with one of these tree clocks (dynamically switchable)?

If the Transmit PLL uses the 150MHz as source to make the line-rate clocks, then the rate at which the TX Phase Compensation fifo is read is also synchronous to this clock. So when I use the 150MHz clock (or a divided 75MHz or 37.5MHz) to write the fifo, I will be frequency syncrhonous. But the phase relation is unknown. Does the TX Phase Compensation fifo tollerate all kinds of phase differences, without knowing the relastion in advance? Do I have to start the fifo in same special way to make shure it is filled to the correct level?

I appriciate very much if somebody can advise me or point me into the right direction.

thanks