How to clock this Tranceivers based design?

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Yes, I can do that for the fifo a need in the receive lane. But the clock input of the Tranceiver (the tx_coreclk) does not come with a enable input. So I will have to dynamical switch the clock between the 3 frequencies. Is that possible in an Altera FPGA?

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For coreclk I don't think you can do that. As stated by Jacobjones you can go for highest data rate and use oversampling on lower data rates to bring them to the high rate but discard the nonvalid data bits. Oversampling ave been discussed in some previous posts