How to clock this Tranceivers based design?

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If your problem is how to clock the fifo then a simple solution is to use the 150MHz for all cases but switch a clock enable which will be high always for 150MHz, divided for the other two cases. I am sure your fifo will have clock enable port.

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Yes, I can do that for the fifo a need in the receive lane. But the clock input of the Tranceiver (the tx_coreclk) does not come with a enable input. So I will have to dynamical switch the clock between the 3 frequencies. Is that possible in an Altera FPGA?