How to check which FPGA is assembled on the pcb?

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Is it possible to read part number of the device before microprocessor starts configuring it?

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If you have JTAG connected to your processor, then that would be easiest. Its pretty easy to read the IDCODE or USERCODE via JTAG - you just bit-bang the JTAG TAP machine into the appropriate state and read out the data.

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But any other ways? Maybe there is another way to check if FPGA assembled on the board and programming data stored in external memory match? Of course microprocessor has to do that.

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On designs that I can load different FPGAs I add 0402 stuff resistors across the BGA pads on the bottom side of the PCB (so that no routing is required). I then load different stuff resistors for the board revision, device type, and FPGA number (because I have multiple FPGAs).

Cheers,

Dave

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If you have JTAG connected to your processor, then that would be easiest. Its pretty easy to read the IDCODE or USERCODE via JTAG - you just bit-bang the JTAG TAP machine into the appropriate state and read out the data.

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But the IDCODE is not unique for each part. I don't know about the Cyclone V's mentioned, but when you use jtagconfig you see a list of candidates for the given ID:

02A030DD 5AGT(FD3H3|MD3G3)/5AGXBB3D4/..

029030DD 5SGXEA7H(1|2|2ES|3|3ES)/..

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But the IDCODE is not unique for each part. I don't know about the Cyclone V's mentioned, but when you use jtagconfig you see a list of candidates for the given ID

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That's a good point actually. Someone at Altera has been screwing up and not changing the JTAG IDCODE on devices.

Though in this particular case, so long as the list of devices that can possibly be loaded on the PCB do not have duplicate IDCODEs, then reading the IDCODE could be used to determine which unique part was loaded. If however the IDCODEs are not unique, then a resistor stuff option that the microcontroller can read *BEFORE* the FPGA is configured would be needed. Although if the resistors were connected to FPGA pins, you could perform a boundary scan of the FPGA to read those pins, before configuring the device.

Cheers,

Dave

I think IDCODE is good enough to narrow down the capacity and flavor of device within a family, but it doesn't include device speed grade information or temperature range.

http://www.altera.com/literature/hb/cyclone-v/cv_52009.pdf

"the idcode is unique for each cyclone v device. use this code to identify the devices in a jtag chain."

Thanks for suggestions.

I have found document: jtag boundary-scan testing in cyclone v devices (http://www.altera.com/literature/hb/cyclone-v/cv_52009.pdf). Table 9-1 (page 1) shows that every Cyclone V device has unique IDCODE, so I think I can use it in my projects.

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On designs that I can load different FPGAs I add 0402 stuff resistors across the BGA pads on the bottom side of the PCB (so that no routing is required). I then load different stuff resistors for the board revision, device type, and FPGA number (because I have multiple FPGAs).

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If however the IDCODEs are not unique, then a resistor stuff option that the microcontroller can read *BEFORE* the FPGA is configured would be needed. Although if the resistors were connected to FPGA pins, you could perform a boundary scan of the FPGA to read those pins, before configuring the device.

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Dave, could you explain more details? Because it is not clear for me. Between which pads do you add resistors? How are they read by uP?

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Dave, could you explain more details? Because it is not clear for me. Between which pads do you add resistors? How are they read by uP?

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Go take a look at this board:

http://www.ovro.caltech.edu/~dwh/carma_board/

Click on the PDF for the schematic:

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

p50: You will see the SYS-FPGA ID code resistors

p57: You will see the DATA-FPGA ID code resistors

What does this look like on an FPGA? Look at this image;

https://www.alteraforum.com/forum/attachment.php?attachmentid=8760

The blue components between BGA pins are resistors. The other components are decoupling capacitors.

The addition of the ID registers "costs nothing", since you can use I/O pads that might otherwise be difficult to get to, eg., they're near the center of the BGA.

In my system, the SYS-ID stuff resistors tell the PowerPC processor which DATA-FPGAs are loaded; Stratix II EP2S90 or EP2S130 devices. The SYS-FPGA then configures the four DATA-FPGAs. The pinouts of those four FPGAs are almost identical. The ID pins are in the same location, as are the inter-FPGA buses. To ensure there is no possibility of bus conflict, each configuration reads the DATA-FPGA-ID stuff resistors and checks that the value matches what they expect, eg., the configurations for DATA-FPGA#0, 1, 2, 3 expect IDs of# 0, 1, 2, 3. If the IDs do not match, then the inter-FPGA buses are not enabled. For a 'basic' configuration, I can load the same design into all four FPGAs.

Cheers,

Dave