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Dave, could you explain more details? Because it is not clear for me. Between which pads do you add resistors? How are they read by uP?
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Go take a look at this board:
http://www.ovro.caltech.edu/~dwh/carma_board/ Click on the PDF for the schematic:
http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf p50: You will see the SYS-FPGA ID code resistors
p57: You will see the DATA-FPGA ID code resistors
What does this look like on an FPGA? Look at this image;
https://www.alteraforum.com/forum/attachment.php?attachmentid=8760 The blue components between BGA pins are resistors. The other components are decoupling capacitors.
The addition of the ID registers "costs nothing", since you can use I/O pads that might otherwise be difficult to get to, eg., they're near the center of the BGA.
In my system, the SYS-ID stuff resistors tell the PowerPC processor which DATA-FPGAs are loaded; Stratix II EP2S90 or EP2S130 devices. The SYS-FPGA then configures the four DATA-FPGAs. The pinouts of those four FPGAs are almost identical. The ID pins are in the same location, as are the inter-FPGA buses. To ensure there is no possibility of bus conflict, each configuration reads the DATA-FPGA-ID stuff resistors and checks that the value matches what they expect, eg., the configurations for DATA-FPGA#0, 1, 2, 3 expect IDs of# 0, 1, 2, 3. If the IDs do not match, then the inter-FPGA buses are not enabled. For a 'basic' configuration, I can load the same design into all four FPGAs.
Cheers,
Dave
Honored Contributor
