How to check clocks using SignalTap II Logic Analyzer?

jtag_debug_sample_clock does just that, it reads the clock signal at the time you ask for it, so sometimes you'll get a 0 and sometimes you'll get a 1.

jtag_debug_sense_clock returns 1 if the clock toggled since the last time you called jtag_debug_sense_clock and 0 otherwise. You may get a 0 after the first call (I never did, but you never know) but after that you should only get 1's. If you get 0's after then you probably have a problem.

In SignalTap if the clock you selected a a sampling clock isn't toggling, SignalTap will tell you so. (I don't remember the exact message, but it's different than 'waiting for trigger')

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To see the clock in the Signal-tap A higher sampling input is needed to sample may be (3 to 4 times more frequency than the clock you want to see)

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Thanks kalyansrinivasm for your advice. How do you come to know that the sampling clock must be 3 to 4 times higher in freq, if it is stated somewhere or just your experience?

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jtag_debug_sample_clock does just that, it reads the clock signal at the time you ask for it, so sometimes you'll get a 0 and sometimes you'll get a 1.

jtag_debug_sense_clock returns 1 if the clock toggled since the last time you called jtag_debug_sense_clock and 0 otherwise. You may get a 0 after the first call (I never did, but you never know) but after that you should only get 1's. If you get 0's after then you probably have a problem.

In SignalTap if the clock you selected a a sampling clock isn't toggling, SignalTap will tell you so. (I don't remember the exact message, but it's different than 'waiting for trigger')

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Thanks Daixiwen very much. I wonder if we can set the sampling time for reading clock? and what is the default time interval if I just invoke two consecutive sample_clock commands, is it in ns or ms?

is it possible to calculate the clock frequency through the results of jtag_debug service?

Thanks.

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is it possible to calculate the clock frequency through the results of jtag_debug service?

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Here's how I test clocks;

1) Create a basic design where an LED blinks at about 1 Hz. If the board has more than one clock, then assign an LED (or two) to each clock.

2) Create a JTAG-to-Avalon-MM design with a clock-counting register block. The clock counter component contains several counters each clocked by an external source. The counters each have an enable input. The enable input comes from an Avalon control register, and is synchronized to each of the respective clock domains. You pulse the enable signal using JTAG commands, and then read out the counter values.

The counter value for the Avalon clock is your reference clock count, eg., lets say I used a 50MHz on-board oscillator for the Avalon clock, the assumption is that that oscillator is exactly 50MHz.

Read the counts in the other counters, and scale them from count to MHz using the reference count.

This is very handy for checking that your PLLs and transceiver clocks are operating at the right frequencies.

Cheers,

Dave

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How do you come to know that the sampling clock must be 3 to 4 times higher in freq, if it is stated somewhere or just your experience

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From Nyquist principle any signal should be sampled more than twice its operating frequency

So for better results sample it using 3 to 4 times higher frequency clock.

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Here's how I test clocks;

1) Create a basic design where an LED blinks at about 1 Hz. If the board has more than one clock, then assign an LED (or two) to each clock.

2) Create a JTAG-to-Avalon-MM design with a clock-counting register block. The clock counter component contains several counters each clocked by an external source. The counters each have an enable input. The enable input comes from an Avalon control register, and is synchronized to each of the respective clock domains. You pulse the enable signal using JTAG commands, and then read out the counter values.

The counter value for the Avalon clock is your reference clock count, eg., lets say I used a 50MHz on-board oscillator for the Avalon clock, the assumption is that that oscillator is exactly 50MHz.

Read the counts in the other counters, and scale them from count to MHz using the reference count.

This is very handy for checking that your PLLs and transceiver clocks are operating at the right frequencies.

Cheers,

Dave

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Thanks Dave. I will try this soon.

By now, I am playing with the SignalTap Analyzer to test clocks by relative comparison. Again, my purpose is to have a synchronous clock for dual-board designs. So, I assign clock like this. The design on the board#1(with the SMA clock output) has input clock assigned to an FPGA pin. This clock is also assigned to the output clock. The design on the board#2 (with the SMA clock input) uses the SMA input clock as the reference.

And something strange happened I don't understand. I use Sinaltap to capture the input clock and output clock in design#1, they are identical. In the board#2, for comparison purpose, I tap the external input clock (coming from board#1 via SMA connectors). and a local clock signal with exactly same frequency (100MHz). But the external input clock is strange, not stable, having too many bit 1s and only 1 bit 0 in a period, while the expected clock should have a duty cycle of 50% (like 1111000011110000).

If anyone has experienced something similar, please share your solution? Or if the quality of SMA cables can be the reason?

Thank you.

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So, I assign clock like this. The design on the board#1(with the SMA clock output) has input clock assigned to an FPGA pin. This clock is also assigned to the output clock. The design on the board#2 (with the SMA clock input) uses the SMA input clock as the reference.

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Ok, good.

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And something strange happened I don't understand. I use Sinaltap to capture the input clock and output clock in design#1, they are identical.

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What is your SignalTap II clock reference on Board#1?

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In the board#2, for comparison purpose, I tap the external input clock (coming from board#1 via SMA connectors). and a local clock signal with exactly same frequency (100MHz).

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Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other.

Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2.

Using counters is much more reliable, since the logic operates in its own respective clock domain.

Cheers,

Dave

Thanks Dave,

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What is your SignalTap II clock reference on Board#1?

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I also use 100MHz clock as clock reference in board#1. In both sides, I use another clock for sampling in signaltap II is 576 MHz.

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Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other

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I did this because first, I want to see if the period and the shape of the two clocks look similar in terms of visualization (normal eyes). And the fact that they looked totally different makes me believe that there exist some problem. And I don't know where it can come from. Do you have an idea?

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Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2.

Using counters is much more reliable, since the logic operates in its own respective clock domain.

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Ok, I got this and will implement this.

Thank you.

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I use another clock for sampling in signaltap II is 576 MHz.

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Ok, so you should see something that looks like a square wave then.

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I did this because first, I want to see if the period and the shape of the two clocks look similar in terms of visualization (normal eyes).

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You won't see that with SignalTap. You need a scope for that sort of visualization.

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And the fact that they looked totally different makes me believe that there exist some problem. And I don't know where it can come from. Do you have an idea?

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Look at the clock output with an oscilloscope. Look at the schematic.

Is the SMA output clock direct from an FPGA pin or does it have a series termination resistor?

Is the SMA input clock direct to an FPGA pin or does it have a buffer between the SMA and the FPGA or does it have a termination resistor? Is it AC coupled or DC coupled? Have you terminated the transmission line correctly, eg., enable a parallel termination if an external one does not exist?

That's a few things for you to think about.

Cheers,

Dave