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So, I assign clock like this. The design on the board#1(with the SMA clock output) has input clock assigned to an FPGA pin. This clock is also assigned to the output clock. The design on the board#2 (with the SMA clock input) uses the SMA input clock as the reference.
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Ok, good.
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And something strange happened I don't understand. I use Sinaltap to capture the input clock and output clock in design#1, they are identical.
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What is your SignalTap II clock reference on Board#1?
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In the board#2, for comparison purpose, I tap the external input clock (coming from board#1 via SMA connectors). and a local clock signal with exactly same frequency (100MHz).
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Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other.
Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2.
Using counters is much more reliable, since the logic operates in its own respective clock domain.
Cheers,
Dave
Honored Contributor
