Honored Contributor
Honored ContributorThanks Dave,
--- Quote Start --- What is your SignalTap II clock reference on Board#1? --- Quote End --- I also use 100MHz clock as clock reference in board#1. In both sides, I use another clock for sampling in signaltap II is 576 MHz. --- Quote Start --- Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other --- Quote End --- . I did this because first, I want to see if the period and the shape of the two clocks look similar in terms of visualization (normal eyes). And the fact that they looked totally different makes me believe that there exist some problem. And I don't know where it can come from. Do you have an idea? --- Quote Start --- Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2. Using counters is much more reliable, since the logic operates in its own respective clock domain. --- Quote End --- Ok, I got this and will implement this. Thank you.
