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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

how to bypass IO limit to get a utilization summary?

Hi,

I wish to get a rough idea of how many registers and ALMs the design takes on Stratix V.

It has passed the Analysis and Synthesis, yet in fitter it stopped with the following error:

Error (169281): There are 3754 IO input pads in the design, but only 968 IO input pad locations available on the device.

Error (169282): There are 4352 IO output pads in the design, but only 968 IO output pad locations available on the device.

It's a design with large number of IOs and I don't want to add the shim at the moment, can anyone suggest a way to bypass the error, just to get a rough number?

Without solving the error, the number of registers yield in fitter summary is unreasonably small.....I assume this has something to do with the IO problem.

Thanks!!!!!!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Yes, a quick and dirty way is to create a new module which takes all, or just some, of your I/Os as inputs/outputs (for example, of some combinatorial operation), to reduce the number of ports which need to be mapped to available pins by the fitter. At the end, just look at the resource utilisation and subtract whatever is used by the "helper" module. Be aware however, that the real resource count depends also on routing and placement and you will not be able to get a perfectly accurate resource count using this method. The correct way is to use design partitions with virtual pins, to achieve the closest resemblance to the final fit/place of your logic without having the whole design in place - but this is too much to explain in a forum post. Quartus Handbook has all the details on how to do it if you are interested.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I've no experience with such a large design, but for smaller ones I make pins virtual by prepending 'v_' to all relevant pins and use the Assignment Editor to add a 'Virtual pin' assignment to 'v_*' pins.

    Don't create entities grouping I/O: the compiler will use depencies on the few pins that remain to to synthesize large parts of the design away. Virtual pins tell it not to have any assumptions about the signal on that pin.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Virtual pins are the answer.

    The quick way to assign them all without any IO pins is just assign * to virtual pin.
    • TRoa's avatar
      TRoa
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      And how to assign to virtual pin? The issue is I can not find this virtual pin option in there. Can anybody tell please. Thanks