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Altera_Forum
Honored Contributor
11 years agohow to bypass IO limit to get a utilization summary?
Hi, I wish to get a rough idea of how many registers and ALMs the design takes on Stratix V. It has passed the Analysis and Synthesis, yet in fitter it stopped with the following error: ...
Altera_Forum
Honored Contributor
11 years agoI've no experience with such a large design, but for smaller ones I make pins virtual by prepending 'v_' to all relevant pins and use the Assignment Editor to add a 'Virtual pin' assignment to 'v_*' pins.
Don't create entities grouping I/O: the compiler will use depencies on the few pins that remain to to synthesize large parts of the design away. Virtual pins tell it not to have any assumptions about the signal on that pin.