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Altera_Forum's avatar
Altera_Forum
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16 years ago

How much is the maximum current of FPGA

Hi,everyone,

I'm working in a project using EP1C6Q240.The datasheet says that the Current Strength of each I/O pin can be set up to 24mA.Suppose I use 100 pins to output 20mA at the same time,the total current that the chip output is 20mA*100=2A.I wonder if the chip can be used like this.:confused: .I don't know whether the datasheet have mentioned it,but I can't found the information.If you know something about it,tell me please.

Thanks.

:)

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What is it you are trying to calculate? The spec you are referring to is simply to indicate that the maximum current each I/O pin can source/sink is 20mA. Beyond that you will damage the FPGA. The amount of current actually drawn by the I/O pin depends on what you've got connected to it.

    Now if you are trying to figure out how much current your FPGA is going to draw in your design so that you can figure out how much power to provide it, that is a much more complicated issue. Altera provides tools that allow you to estimate the power consumption of your design and figure out how large to make your power supplies.

    The best one is the PowerPlay power estimator built into the Quartus II software.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,Jack,

    The maximum current is 24mA,I am sure.

    I just suppose that I use all I/O pin to source/sink the same current(20mA,for example).The amount of current actually drawn by the I/O pin depends on what you've got connected to it,you are right.And I suppose in my curcuit the current is 20mA.The problem is,if I use many pins in this way,the sum of the current count be great,and I wonder if the FPGA would damage.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can also perform advanced I/O analysis where you state specifically what the loading on the pins are. This enables Quartus to warn you of any problems.

    Are you driving LEDs with the pins? What I typically recommend is that you drive LEDs through a standard LVTTL or LVCMOS buffer (like a 74LVT244 for example). It's not worth risking damage to your FPGA.

    What are you doing that has such a high current requirement on the pin?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I use 74LVTH16245 and ULN2803 in our former design to decrease power consumption in FPGA.I know it's a better choice.I just want to know whether there is a constraint:confused: .Some MCU's pin can source/sink dozens of mA,but the summation of the current is limited to hundreds of mA,even if it has lots of pins.Did you want to tell me that I can't calculate the total current by adding each current of I/O simply,But to use something like advanced I/O analysis? I know nothing about it.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As already said, current strength doesn't involve safe current limit. You have to care for a safe external circuitry. The Cyclone handbook is clear regarding permitted DC loads, in my opinion. The 25 mA limit value would be allowed for all output pins simulataneously, because the supplementing current per pin group limitation is even higher.

    But, if the 20 mA per pin is a high speed dynamic load, there's a good chance for your design to fail due to SSO (simultaneous switching outputs) noise, particularly with a Q240 package.