how do I generate 32k clock from cyclone V pll

@ak6dn Doesn't work like that... The first multiply/divide counter (M/N) sets the VCO frequency. The VCO frequency must be at least 600MHz.

The lowest frequency the PLL output will do is around 1.6MHz. For lower clock frequencies, this should be done in logic, either to make a clock enable, or a low frequency clock as I said in my earlier post.

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@ak6dn Doesn't work like that... The first multiply/divide counter (M/N) sets the VCO frequency. The VCO frequency must be at least 600MHz.

The lowest frequency the PLL output will do is around 1.6MHz. For lower clock frequencies, this should be done in logic, either to make a clock enable, or a low frequency clock as I said in my earlier post.

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That is true for a single, direct PLL output clock. However, for Cyclone V you can use 'cascade counter mode' where you take pll_output_0 at 8.0MHz, for example, and use that as the source clock to pll_output_1 in cascade mode, and then set the divisor to (in this case 250) to generate 8MHz/250 = 32KHz on pll_output_1. It takes two PLL outputs to do this, but it allows for much higher clock division ratios (ie, up to 512*512).

Reference, ALTPLL IP User Guide, version 2014-08-18, page 28:

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pll output counter cascading

In 28 nm devices, a C-counter input can be either a VCO output or the cascaded output of a neighboring

C-counter. Cascading C-counters increase the possible division factor, enabling very low frequency PLL

output clocks.

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In the QSYS IP wizard, select two PLL clock outputs, and tick the 'cascade mode' box on output 0 to feed it into output 1 source.

Ok, here it is in Quartus 16.0:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12556&stc=1

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The device handbook describes the limits for the PLL constants. You must stay within those limits. I suspect 250 is too large a divisor.

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Hi,

Thanks for the replying. every one here is correct but I find when I choose "Enable physical output clock parameters" which can show M,N.C values, it doesn't allow me to "finish". Does any one know why?

Thanks,

Jeff

It should be generating an error message in the 'message' window if it does not like some parameter value or values.

You might have to take a screen shot of the problematic window and post it.

What version of Quartus are you using?

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That is true for a single, direct PLL output clock. However, for Cyclone V you can use 'cascade counter mode' where you take pll_output_0 at 8.0MHz, for example, and use that as the source clock to pll_output_1 in cascade mode, and then set the divisor to (in this case 250) to generate 8MHz/250 = 32KHz on pll_output_1. It takes two PLL outputs to do this, but it allows for much higher clock division ratios (ie, up to 512*512).

Reference, ALTPLL IP User Guide, version 2014-08-18, page 28:

In the QSYS IP wizard, select two PLL clock outputs, and tick the 'cascade mode' box on output 0 to feed it into output 1 source.

Ok, here it is in Quartus 16.0:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12556&stc=1

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Hi,

I got it. Thanks a lot.

-Jeff

Hi,

I got 32k finally. Thanks everyone.

-Jeff

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@ak6dn. Did not know that. Thanks, very informative! :)

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Altera does not always make it easy to find new and useful features :(