how do I generate 32k clock from cyclone V pll

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The device handbook describes the limits for the PLL constants. You must stay within those limits. I suspect 250 is too large a divisor.

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Hi,

Thanks for the replying. every one here is correct but I find when I choose "Enable physical output clock parameters" which can show M,N.C values, it doesn't allow me to "finish". Does any one know why?

Thanks,

Jeff