how do I generate 32k clock from cyclone V pll

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That is true for a single, direct PLL output clock. However, for Cyclone V you can use 'cascade counter mode' where you take pll_output_0 at 8.0MHz, for example, and use that as the source clock to pll_output_1 in cascade mode, and then set the divisor to (in this case 250) to generate 8MHz/250 = 32KHz on pll_output_1. It takes two PLL outputs to do this, but it allows for much higher clock division ratios (ie, up to 512*512).

Reference, ALTPLL IP User Guide, version 2014-08-18, page 28:

In the QSYS IP wizard, select two PLL clock outputs, and tick the 'cascade mode' box on output 0 to feed it into output 1 source.

Ok, here it is in Quartus 16.0:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12556&stc=1

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Hi,

I got it. Thanks a lot.

-Jeff