how do I generate 32k clock from cyclone V pll

@ak6dn Doesn't work like that... The first multiply/divide counter (M/N) sets the VCO frequency. The VCO frequency must be at least 600MHz.

The lowest frequency the PLL output will do is around 1.6MHz. For lower clock frequencies, this should be done in logic, either to make a clock enable, or a low frequency clock as I said in my earlier post.