How do I cascade two PLLs?

derive_pll_clocks constraints the PLLs in a "self-contained" way. For example, if PLL clk2 output does a 2x clock, then the create_generated_clock assignment basically says, "I am 2x of whatever clock comes into the PLL". This way the first PLL doesn't need to know the name of the port driving it that you put the create_clock on, and the second PLL doesn't need to know that it's being driven by a PLL. It's designed to "just work". Without any more details, I'm assuming it's correct.

The one that that may occur is your outputs of the second PLL are not exactly in phase with the first PLL. So there will be skew on transfers between the PLLs which can cause issues. This isn't a constraint issue, but the physical design. But without more info, it's hard to say why it's failing. When you look at the failing path, does the constraint(setup relationship?) seem wrong? What about the clock skew? Once those are ruled out, it's the data path.

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derive_pll_clocks constraints the PLLs in a "self-contained" way. For example, if PLL clk2 output does a 2x clock, then the create_generated_clock assignment basically says, "I am 2x of whatever clock comes into the PLL". This way the first PLL doesn't need to know the name of the port driving it that you put the create_clock on, and the second PLL doesn't need to know that it's being driven by a PLL. It's designed to "just work". Without any more details, I'm assuming it's correct.

The one that that may occur is your outputs of the second PLL are not exactly in phase with the first PLL. So there will be skew on transfers between the PLLs which can cause issues. This isn't a constraint issue, but the physical design. But without more info, it's hard to say why it's failing. When you look at the failing path, does the constraint(setup relationship?) seem wrong? What about the clock skew? Once those are ruled out, it's the data path.

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Thanks - but useful as the answer is, it doesn't match my question 8-}. The first PLL drives ONLY the 2nd PLL. My problem is that if I just connect them together, and specify the input clock, and "derive pll clocks", TimeQuest seems to ignore the constraints. If I try to put the "create_generated_clock" constraints in explicitly, and comment out derive_pll_clocks - it complains of duplicate constraints (as if the derive_pll_clocks is still there).

can someone who has done this successfully show me how they did it?

Thanks!

/j

Once I routed the first pll output to clock output pin, which was connected to clock input pin of second pll. This worked fine, although I didn't measure the jitter performance of the second pll.

-Topi

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Once I routed the first pll output to clock output pin, which was connected to clock input pin of second pll. This worked fine, although I didn't measure the jitter performance of the second pll.

-Topi

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what did your .sdc file look like? did you specify anything other than the input to the first PLL?

Example:

50 MHz crystal going to PLL1 reference.

PLL1 setup has c0 output fror 75 MHz, and reference frequency of 50 MHz.

PLL2 setup has 75 MHz reference, and c0 output for 62.5 MHz.

The in SDC:

derive_pll_clocks -create_base_clocks

Which generates derived clocks (2 of them) and base clocks (2 of them).

But the SDC does not know the phase relationship between 50 MHz and 62.5 MHz. For that, something more needs to be told for SDC, which I don't know at the moment.

-Topi

Thanks, I understand your issue, and FWIW I think I saw some mention of it in the manual for the PLL Megafunction. I don't have that need though, so this helps a lot

best

/j