How do I cascade two PLLs?

derive_pll_clocks constraints the PLLs in a "self-contained" way. For example, if PLL clk2 output does a 2x clock, then the create_generated_clock assignment basically says, "I am 2x of whatever clock comes into the PLL". This way the first PLL doesn't need to know the name of the port driving it that you put the create_clock on, and the second PLL doesn't need to know that it's being driven by a PLL. It's designed to "just work". Without any more details, I'm assuming it's correct.

The one that that may occur is your outputs of the second PLL are not exactly in phase with the first PLL. So there will be skew on transfers between the PLLs which can cause issues. This isn't a constraint issue, but the physical design. But without more info, it's hard to say why it's failing. When you look at the failing path, does the constraint(setup relationship?) seem wrong? What about the clock skew? Once those are ruled out, it's the data path.