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Altera_Forum's avatar
Altera_Forum
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13 years ago

how can we enable and disable the particular modules we need in verilog?

i need to enable a particular module when some condition is satisfied and each module is selected on particular condition...i have written different modules now and i need to write a top module to connect all these modules under it...can you guys help me to solve this issue?....i tried to instantiate it in case statement but it s showing error...

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Use a Generate statement:

    generate

    if (someparam == 1) begin

    module module_i (

    ports

    );

    end

    endgenerate
  • Altera_Forum's avatar
    Altera_Forum
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    Don't expect further help if you don't provide more information about the error

  • Altera_Forum's avatar
    Altera_Forum
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    this is the sample code i hav written...please check for an error ...

    module arithmetic20(A,B,S,out);

    input A,B;

    input [1:0]S;

    output out;

    generate

    if(S==2'b00)

    begin

    and1 a1(A,B,out);

    end

    endgenerate

    generate

    if(S==2'b01)

    begin

    or1 o1(A,B,out);

    end

    endgenerate

    generate

    if(S==2'b10)

    begin

    xor1 x1(A,B,out);

    end

    endgenerate

    generate

    if(S==2'b11)

    begin

    nor1 n1(A,B,out);

    end

    endgenerate

    endmodule

    module and1(A,B,out);

    input A,B;

    output out;

    wire out;

    assign out=A&B;

    endmodule

    module or1(A,B,out);

    input A,B;

    output out;

    wire out;

    assign out=(A|B);

    endmodule

    module xor1(A,B,out);

    input A,B;

    output out;

    wire out;

    assign out=(A^B);

    endmodule

    module nor1(A,B,out);

    input A,B;

    output out;

    wire out;

    assign out=(~(A|B));

    endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    Generates will only work with static parameters define at synthesis time. So this won't work for you. What you could do is simply:

    assign out = (S == 2'b00) ? A&B :

    (S == 2'b01) ? A| B :

    (S == 2'b10) ? A^B : ~(A|B );
  • Altera_Forum's avatar
    Altera_Forum
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    what you are saying is correct...the above is just an example...i have to make a control unit for alu...in alu i have done adder,multiplication and logical modules written separately in gate level...