Forum Discussion
Altera_Forum
Honored Contributor
13 years agohow can we enable and disable the particular modules we need in verilog?
i need to enable a particular module when some condition is satisfied and each module is selected on particular condition...i have written different modules now and i need to write a top module to co...
Altera_Forum
Honored Contributor
13 years agoUse a Generate statement:
generate if (someparam == 1) begin module module_i ( ports ); end endgenerate