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Altera_Forum's avatar
Altera_Forum
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13 years ago

how can we enable and disable the particular modules we need in verilog?

i need to enable a particular module when some condition is satisfied and each module is selected on particular condition...i have written different modules now and i need to write a top module to co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Generates will only work with static parameters define at synthesis time. So this won't work for you. What you could do is simply:

assign out = (S == 2'b00) ? A&B :

(S == 2'b01) ? A| B :

(S == 2'b10) ? A^B : ~(A|B );