how can we enable and disable the particular modules we need in verilog?

this is the sample code i hav written...please check for an error ...

module arithmetic20(A,B,S,out);

input A,B;

input [1:0]S;

output out;

generate

if(S==2'b00)

begin

and1 a1(A,B,out);

end

endgenerate

generate

if(S==2'b01)

begin

or1 o1(A,B,out);

end

endgenerate

generate

if(S==2'b10)

begin

xor1 x1(A,B,out);

end

endgenerate

generate

if(S==2'b11)

begin

nor1 n1(A,B,out);

end

endgenerate

endmodule

module and1(A,B,out);

input A,B;

output out;

wire out;

assign out=A&B;

endmodule

module or1(A,B,out);

input A,B;

output out;

wire out;

assign out=(A|B);

endmodule

module xor1(A,B,out);

input A,B;

output out;

wire out;

assign out=(A^B);

endmodule

module nor1(A,B,out);

input A,B;

output out;

wire out;

assign out=(~(A|B));

endmodule