New Contributorhow can I do a pin planner assignment follow the Intel Cyclone 10 GX Schematic?
I'm using Cyclone 10GX development kit to develop a project. I downloaded the Cyclone 10 GX Schematic which shows the Cyclone 10 LP FPGA development kit board. Are these two boards sharing the same Schematic? If the Schematic is correct, how to Assign the pin planner to the schematic?
for example, these two pins are different between the bts_config_pinplanner and schematic.
c10_clk50m is PIN_J23 in bts_config_pinplanner but E1 CLK1, DIFFCLK_0N in schematic.
USER_LED0 is PIN_AF6 in bts_config_pinplanner but L14 IO, VREFB5N0 in schematic.
I want to use S13 defined ug-c10-gx-fpga-devl-kit.pdf:S13 C10_RESETn_PB Trigger logic reset to Intel Cyclone 10 GX FPGA logic. The state of the configured logic is reset, the configuration remains unchanged.
C10_RESETTN is not set in bts_config_pinplanner but is J15, DIFFIO_R9N,DEV_OE in schematic
