How can I design a 2 BIT ADDER using AHDL

Unless you are being forced to use AHDL then I would pick a modern language like verilog or VHDL. For example this is much easier (verilog)

assign sum = a + b;

.... that's it, if you wanted to do this two one bit adders you would code up the individual sum bits and carries manually.

You can do anything in AHDL like you could in Verilog or VHDL. Just with a lot less typing. But the drawback is it seems to be a dying langage as it is just used by Altera.

Anyway why not just add.

e.g.

in variables

s[2..0] : NODE;

a[1..0] : NODE;

b[1..0] : NODE;

in main section

s[2..0] = (0,a[1..0]) + (0,b[1..0]) ;

regards

DaveLuscher

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You can do anything in AHDL like you could in Verilog or VHDL.

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How about testbenching? File IO? Behavioural models?

AHDL is just a netlist language, nothing more. Hence it's only good for learning digital circuit design, and not much else.

Well sorry Tricky if I rattled your cage, but the question was adder using AHDL.

I would agree that one of the other text entry methods are what he should be learning.

Hey guys,

I just wanted to say thanks to both you and that is exactly what I needed it for Tricky I am learning circuit design. But what I have been getting confused is, I thought Altera was like Multisim by EWB, and I could actually see the actual components in action. I guess I am learning the hard way that is not the case huh. The only thing I am getting out of this is a signal trace or should I be seeing something else?

Lew

Altera is a company that makes FPGAs (field programmable gate arrays - esensially reporgrammable circuits). Quartus is nothing more than a compiler to get your code onto this chip.

Modelsim is a separate program by a sepearate company (mentor) that can be used to simulate code in its text form, but you cant do this with AHDL (because it's an old and dying proprietry language). Quartus does have a very basic simulator that lets you simulate compiled designs, but modelsim can do this too, and is much more powerful.

For any designs, all you will ever see is a signal trace - the skill is knowing what stimulus to give it. With modelsim you can design a testbench in VHDL that can produce all manners of stimulus.

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Hey guys,

I just wanted to say thanks to both you and that is exactly what I needed it for Tricky I am learning circuit design. But what I have been getting confused is, I thought Altera was like Multisim by EWB, and I could actually see the actual components in action. I guess I am learning the hard way that is not the case huh. The only thing I am getting out of this is a signal trace or should I be seeing something else?

Lew

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It's a bit different, in Multisim you build up circuits in schematics and simulate everything in the same program. It's really a GUI frontend for SPICE models of various components. In the end you would still need to take what you designed in Multisim and translated it into physical circuits.

Quartus II is a compiler amongst other things and to see your logic operate you need to simulate it. The compiled logic can be downloaded into a "blank" FPGA and it will behave as whatever you programmed it with. So once your logic is designed you would create a testbench with stimulus to see how the logic behaves. The reason for this is it's pretty difficult to get a good idea how everything is working at any given time using just trace alone. The typical design flow is like this:

Design logic --> Compile logic in Quartus/Test logic using a simulation --> Fix bugs --> Compile...... etc...