Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYou can do anything in AHDL like you could in Verilog or VHDL. Just with a lot less typing. But the drawback is it seems to be a dying langage as it is just used by Altera.
Anyway why not just add. e.g. in variables s[2..0] : NODE; a[1..0] : NODE; b[1..0] : NODE; in main section s[2..0] = (0,a[1..0]) + (0,b[1..0]) ; regards DaveLuscher