Hi, I saw some hold time violation when I trying to run the STA. I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3. so is there anything I can do to fix this problem? Thanks!!!!

If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.

--- Quote Start --- If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception. --- Quote End --- The suggestion sounds ambiguous to me. You'll first determine how data can be consistently transferred between both clock domains and design the logic respectively. Then specify appropriate clock constraints. The suggested constraints might fit under circumstances.

--- Quote Start --- Hi, I saw some hold time violation when I trying to run the STA. I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3. so is there anything I can do to fix this problem? Thanks!!!! --- Quote End --- How are the two clocks related? Are they the same frerquency, different phases? Or different frequencies? Derived from same source, or different input sources? If you know enough about the relationship of the clock waveforms you should be able to setup timing relationships for the data transfer (setup, hold, multicycle). Otherwise if the sources are asynchronous you will need to setup a false timing path to remove the timing check (and implement the appropriate synchronizer logic as well).

Hi, the output clock is half frequency of input clock. output clock(100ns), input clock(50ns). when I run RTL simulation, everything looks good. however, when I trying to run gate level simulation, the output clock always shift half clock period to the left. I have set multicycle exception for these two clock,the output clock always delay one input clock period . set_multicycle_path 1 -setup -start -from CLK -to CLK2 set_multicycle_path 0 -hold -start -from CLK -to CLK2 I not sure what the problem is. Thanks!

--- Quote Start --- How are the two clocks related? Are they the same frerquency, different phases? Or different frequencies? Derived from same source, or different input sources? If you know enough about the relationship of the clock waveforms you should be able to setup timing relationships for the data transfer (setup, hold, multicycle). Otherwise if the sources are asynchronous you will need to setup a false timing path to remove the timing check (and implement the appropriate synchronizer logic as well). --- Quote End --- Hi, the output clock is half frequency of input clock. output clock(100ns), input clock(50ns). when I run RTL simulation, everything looks good. however, when I trying to run gate level simulation, the output clock always delay one input clock period . I have set multicycle exception for these two clock, but still see the shift. set_multicycle_path 1 -setup -start -from CLK -to CLK2 set_multicycle_path 0 -hold -start -from CLK -to CLK2 I not sure what the problem is. Thanks!

hold time violation using MAX V | Altera Community

12 Replies

Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.
--- Quote End ---

The suggestion sounds ambiguous to me. You'll first determine how data can be consistently transferred between both clock domains and design the logic respectively. Then specify appropriate clock constraints. The suggested constraints might fit under circumstances.
Altera_Forum
Honored Contributor
9 years ago
If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.

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hold time violation using MAX V

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