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Altera_Forum
Honored Contributor
Honored Contributorhold time violation using MAX V
Hi, I saw some hold time violation when I trying to run the STA. I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thin...
Altera_ForumHonored Contributor
Honored ContributorIf the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.
