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Altera_Forum's avatar
Altera_Forum
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8 years ago

hold time violation using MAX V

Hi, I saw some hold time violation when I trying to run the STA. I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.