hold time violation using MAX V

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If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.

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The suggestion sounds ambiguous to me. You'll first determine how data can be consistently transferred between both clock domains and design the logic respectively. Then specify appropriate clock constraints. The suggested constraints might fit under circumstances.